Prev Page Next Page


Formal Definition

A set of values and a set of operations.

Simplified Syntax

type type_name is type_definition;

type type_name;


Each object in VHDL has to be of some type, which defines possible values and operations that can be performed on this object (and other objects of the same type). The set of operations of a type consists of:

See respective topics for details.

Apart from predefined types (available through the packages Standard and Std_Logic_1164), the user can define his/her own types. A user-defined type can be of any of the four classes mentioned above. The rules for defining types are described in detail in the corresponding topics.

Important Notes

Prev Page Next Page