The Bit type is predefined in the
Standard package as an enumerated data type with only two allowable
values: '0' and '1'.
type bit is ('0','1');
The bit type is the basic
type to represent logical values. Note that there are only two values
defined for the bit type and
it is not possible to use it for high impedance and other non-trivial
values such as Unknown, Resistive Weak, etc. (see Std_logic).
According to the type definition, its leftmost value is '0',
therefore the default value of any object of the bit
type is '0'.
As the bit type is defined
in the Standard package, it can be used in any VHDL specification
without additional declarations.
Signals of the bit type are
not resolved which means that such a signal can be assigned to an
expression only once in the entire architecture.
signal BitSig1, BitSig2 : bit;
. . .
BitSig1 <= '1';
BitSig2 <= not BitSig1;
The BitSig1 and BitSig2 signals are declared without an initial
value, therefore by default they will be assigned the '0' value. In
the next statement BitSig1 is assigned the '1' value. This value is
complemented in the following statement and is assigned to BitSig2.
Any additional assignment either to BitSig1 or BitSig2 would be illegal.
Unlike in traditional ("hand-based") digital design,
logical values 0 and 1 (bit type values '0' and '1') are NOT
identical to boolean values (false
and true), respectively. In
VHDL, the latter items form completely different type (Boolean).
Logical values for object
of the bit type MUST be
written in quotes to distinguish them from Integer