A configuration is a construct
that defines how component instances in a given block are bound to
design entities in order to describe how design entities are put
together to form a complete design.
use entity library_name.entity_name(arch_name);
use configuration library_name.config_name;
Each component instantiation refers to some design entity
(entity/architecture pair) and the association is specified by a configuration
specification. Component specification appears in the
declarative part of the unit, where the instances are used. This way
components can be configured within architecture which instances them
without using a separate configuration declaration. The specification
is simpler, but also less flexible. Example 1 contains a
configuration specification for the same component as in the Example
1 in the configuration declaration description.
When the ports and generics in component declaration do not match
with their counterparts in entity declaration, so called binding
indication can be applied. Simply speaking this is an
explicit notification on how the ports and generics in the entity
should be bound to ports and generics of the component instance. The generic
map and port map
clauses are used for this purpose. This technique is used in Example
1. In practice, however, it is recommended to match the generics and
ports of components and respective entities as this improves readability.
If no configuration (either in the form of a declaration or
specification) is supported for a component, so called default
binding will occur. This means that for such a component an
entity will be selected such that its name, port names, port types,
generics etc. match those in the corresponding component declaration.
If the entity has more than one architecture, the last analyzed of
them will be used.
entity INVERTER is
(PropTime : TIME := 5 ns);
port ( IN1
: in BIT; OUT1 : out BIT);
architecture STRUCT_I of
OUT1 <= not
IN1 after PropTime;
entity TEST_INV is end TEST_INV;
architecture STRUCT_T of
signal S1, S2 : BIT := '1';
-- INV_COMP component declaration:
component INV_COMP is
(TimeH : TIME);
IN_A : in BIT; OUT_A : out
for LH : INV_COMP
-- indicates generic and port aspects:
(PropTime => TimeH)
(IN1 => IN_A, OUT1 => OUT_A);
-- instantiation of INV_COMP component:
LH : INV_COMP generic map
Architecture STRUCT_T of the entity TEST_INV uses a component
INV_COMP. The binding of the component to the entity INVERTER and
architecture STRUCT_I is realized by the configuration specification
which appears in the declarative part of the architecture.
Synthesis tools do generally not support configurations. Users are
required to ensure that component and entity names, ports and
generics match (default binding).
For a configuration of some design entity, both the entity and the
configuration must be declared in the same library.