Entity is the description of the
interface between a design and its external environment. It may also
specify the declarations and statements that are part of the design
entity. A given entity declaration may be shared by many design
entities, each of which has a different architecture. Thus, an entity
declaration can potentially represent a class of design entities,
each having the same interface.
entity entity_name is
end entity entity_name;
An entity specifies the interface between the specified design
(formally called a design entity)
and the environment in which it operates. On the other hand, an architecture
is a description of the inner design operation and it must be
assigned to an entity. The architecture
can be assigned to one entity
only but one entity may be
assigned to a number of architectures.
The entity statement
declares the design name (the identifier
item in the Syntax example). In addition, it defines generic
parameters (see generic)
and ports (see port) of the
design entity. Generic parameters provide static information (like
timing parameters or bus width) to a design. Ports provide
communication channels between the design and its environment. For
each port, its mode (i.e. data flow) and type are defined.
Optionally, an entity may contain a declarative
part. Any subprograms, types, subtypes, and constants can be
Declarations which are defined in an entity
are visible to all architectures assigned to this entity.
An entity may contain its
own statements, declared after the begin
keyword. The statements here must be passive, which means they cannot
alter values of any signals; Passive processes, concurrent assertion
statements and passive concurrent procedure calls can be used here.
The entity declaration may
be preceded by the library
and use clauses. This way
all declarations defined in a package will be visible for the entity
and all architectures assigned
entity BCD_Decoder is
BCD : in
Bit_Vector (2 downto 0);
Enable : in Bit;
LED : out
Std_Ulogic_Vector (3 downto 0));
constant ZERO :
0) := "0000";
assert (BCD /=
"BCD = 7 " severity note;
end entity BCD_Decoder;
The above example illustrates several important issues related to entities.
First two lines contain a call to the IEEE library and to the
std_logic_1164 package, respectively. These two lines are required
because the Std_Ulogic_Vector type used for the output signal LED is
not a standard type but it is defined in the mentioned package. If
LED would be of Bit_Vector type then the two lines could have been omitted.
The BCD_Decoder identifier, which is following the entity keyword, is
a name assigned by the designer to the entity. Note that this name is
repeated at the very end of the entity.
The above listed entity contains the specification of ports only. In
this case there are two inputs (BCD and Enable) and one output (LED).
The mode for each of them is supported after a colon and is followed
by a specification of the signal's type. See ports for more details
on modes and types of ports.
The Declarative part of the above entity contains two declarations:
constant and assert statements. The constant introduced here will be
visible in all architectures of the BCD_Decoder entity. This type of
a declaration makes sense if there are more than one such
architectures. Otherwise, it might be better to place it in the
architecture section to make the entity more clear. See constant for
more details on constants.
The assert statement is a concurrent statement which will be active
whenever any of the BCD_Decoder architectures is active. This
particular statement will generate a Message listed in the report
clause, whenever BCD will be equal to "111" ("BCD =
7"). Note that the condition in the assert statement should be
interpreted as "if not condition - then report". Turn to
assert for more information on this topic.
The VHDL Language Reference Manual uses the name design
entity for a complete specification of the design, i.e. both
its interface (entity unit)
and behaviour or structure (architecture
unit). Therefore entity and design
entity are not the same concepts!
The identifier for an entity must conform to VHDL identifier rules;
it must start with a letter followed by an arbitrary combination of
letters, digits and underline symbols.
While it is not necessary to repeat the name of an entity at the end
of the declaration, it is strongly recommended to do it for the sake
of clarity of the description; for the same reason it is advised to
add the entity keyword
between the end and the entity name.
It is possible to write an entity
without any generics, ports
and passive statements. In
fact this is used in constructing testbenches (see testbench).