A process statement defines an
independent sequential process representing the behavior of some
portion of the design.
[process_label:] process [ (
sensitivity_list ) ] [ is ]
[ process_label ] ;
The process statement represents the behavior of some portion of the
design. It consists of the sequential statements whose execution is
made in order defined by the user.
Each process can be assigned an optional label.
The process declarative part defines local items for the process and
may contain declarations of: subprograms, types, subtypes, constants,
variables, files, aliases, attributes, use clauses and group
declarations. It is not allowed to declare signals or shared
variables inside processes.
The statements, which describe the behavior in a process, are
executed sequentially, in the order in which the designer specifies
them. The execution of statements, however, does not terminate with
the last statement in the process, but is repeated in an infinite
loop. The loop can be suspended
and resumed with wait
statements. When the next statement to be executed is a wait
statement, the process suspends its execution until a condition
supporting the wait statement is met. See respective topics for details.
A process declaration may contain optional sensitivity list. The list
contains identifiers of signals to which the process is sensitive. A
change of a value of any of those signals causes the suspended
process to resume. A sensitivity list is a full equivalent of a wait
on sensitivity_list statement at the end of the process. It
is not allowed, however, to use wait statements and sensitivity list
in the same process. In addition, if a process with a sensitivity
list calls a procedure, then the procedure cannot contain any wait statements.
entity D_FF is
port (D,CLK : in BIT;
Q : out
BIT := '0';
NQ : out
BIT := '1' );
end entity D_FF;
architecture A_RS_FF of
BIN_P_RS_FF: process (CLK)
CLK = '1' and CLK'Event then
Q <= D;
NQ <= not D;
end architecture A_RS_FF;
The flip-flop has two input ports: D, CLK and two output ports: Q and
NQ. The value of the input signal D is assigned to the output Q when
the value of the CLK changes from '0' to '1'. The change of the
signal value initiates the process BIN_P_RS_FF, because the signal
CLK is on the sensitivity list of this process. The change of the CLK
value from the logical zero to the logical one is sensed by the use
of the if statement.
The first part of if statement
takes place when the actual value of the signal CLK is checked. The
second part confirms that the signal CLK really changes its value
(attribute 'Event is responsible for that). In the case when the
logical value of this condition is TRUE, then the two assignment
signal statement are executed.