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Table of Contents
Access Type
Assertion Statement
Attributes (predefined)
Attributes (user-defined)
Block Statement
Case Statement
Character Type
Component Declaration
Component Instantiation
Composite Type
Configuration Declaration
Configuration Specification
Enumeration Type
Exit Statement
File Declaration
File Type
Floating Point Type
Generate Statement
If Statement
Integer Type
Library Clause
Loop Statement
Next Statement
Null Statement
Operator Overloading
Package Body
Physical Type
Process Statement
Record Type
Report Statement
Reserved Word
Resolution Function
Return Statement
Scalar Type
Sensitivity List
Signal Assignment
Signal Declaration
Standard Package
Std_Logic_1164 Package
Type Conversion
Use Clause
Variable Assignment
Variable Declaration
Wait Statement

Signal Declaration

Formal Definition

Signal is an object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations and port declarations.

Simplified Syntax

signal signal_name : type;

signal signal_name : type := initial_value;


Signals are the primary objects describing a hardware system and are equivalent to "wires". They represent communication channels among concurrent statements of system's specification. Signals and associated mechanisms of VHDL (like signal assignment statements, resolution function, delays, etc.) are used to model inherent hardware features such as concurrency, inertial character of signal propagation, buses with multiple driving sources, etc. Each signal has a history of values and may have multiple drivers, each of which has a current value and projected future values. All signal parameters are accessible by means of signal attributes.

Signals can be explicitly declared in the declarative part of:

  • package declaration; signals declared in a package are visible in all design entities using the package (through the use clause);

  • architecture (see architecture); such signals are visible inside the architecture only;

  • block (see block); the scope of such signals is limited to the block itself;

  • subprogram (see function and procedure); such signals are visible in respective subprogram.

Moreover, a port declaration in an entity is an implicit signal declaration (example 1). A signal declared this way is visible in all architectures assigned to that entity.

A signal declaration contains one or more identifiers (i.e. more than one signal can be declared in one statement) and a subtype indicator. Each signal name is an identifier and creates one separate signal. The (sub)type in the signal declaration can be of any scalar or composite type. Optionally, it may have some constraints. File and access types are not allowed for signals. Some typical signal declarations are given in the Example 1, below.

A signal can be assigned an initial (default) value in its declaration. It the value is produced by an expression, it must be of the same type as the signal itself. If there is no expression given in the signal declaration, then the default value of the signal is the left bound of the specified type (see Example 2).

A signal may be declared with a signal_kind statement, which can be either a register or bus. Such signal must be of a resolved type. A register type signal retains its current value even when all its drivers are turned off. However, the signal_kind bus relies on the resolution function to supply a "no-drive" value (see resolution function for details)


Example 1

library IEEE;
use IEEE.Std_Logic_1164.all;
entity DataTransm is
  port (Data : Std_Logic_Vector(15 downto 0));
end entity DataTransm;
architecture ExDecl of DataTransm is
signal Temp : Std_Logic;
signal FlagC, FlagZ : Bit;
  . . .

Each statement of the architecture ExDecl may use any of the four signals: Data (16-bit vector), declared as a port in the entity part (above the architecture section), Temp which is a single signal of the type Std_Logic and two one bit signals: FlagC and FlagZ. Note that the signals FlagC and FlagZ are declared together in the same line because they both are of the same type.

Example 2

type Four_VL is ('X','0','1','Z');
signal Sig1 : Four_VL;
signal Sig2 : Four_VL := 'X';
signal Sig3 : Four_VL := '0';

All three above listed signals are of the same type, but their default values are specified in different ways. Sig1 will be assigned the leftmost value of the type, i.e. 'X' (Leftmost item in the first line), Sig2 is explicitly assigned the same value. However, as this is the leftmost value of the signal type in this assignment, it is redundant and can be omitted. Finally, Sig3 is assigned the '0' value. Since '0' is not the leftmost value of the type, it has to be assigned explicitly to the signal.

Important Notes

  • It is illegal to declare signals in a process or a subprogram (except as formal parameters).

  • Each port specified in an entity is accessible as a signal in every architecture assigned to this entity and need not to be declared again.

  • A signal may never be of a file or access type.

  • Despite that value assignment to a signal is made with the '<=' symbol, it is not applicable to the default value listed in the signal declaration, where the ':=' symbol must be used.

  • If a signal is to be driven by more than one source (i.e. it will be assigned values in more than one statement), it has to be declared as of resolved type (see resolution and driver).

  • The signal_kinds (register and bus) are not supported by synthesis tools.


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