Package Std_Logic_1164 is NOT a
part of the VHDL Standard Definition. It is defined as IEEE Std 1164.
The Std_Logic_1164 Package contains definitions of types, subtypes,
and functions, which extend the VHDL into a multi-value logic. It is
not a part of the VHDL Standard, but it is a separate Standard of the
same standardization body (Institute of Electrical and Electronics
Main reason for development and standardization of Std_Logic_1164 was
the need for more logical values (than the two defined by the type
Bit in the Standard package) with resolution function. The types
Std_Logic and Std_Logic_Vector (declared in Std_Logic_1164 package)
became de facto industrial standards.
The package contains the following declarations:
type std_ulogic: unresolved
logic type of 9 values;
vector of std_ulogic;
function resolved resolving
a std_ulogic_vector into std_ulogic;
subtype std_logic as a
resolved version of std_ulogic;
vector of std_logic;
subtypes X01, X01Z,
subtypes of resolved std_ulogic containing the values listed in the
names of subtypes (i.e. UX01 contains values 'U', 'X', '0', and '1', etc.);
logical functions for std_logic, std_ulogic, std_logic_vector and std_ulogic_vector;
conversion functions between std_ulogic and bit, std_ulogic and
bit_vector, std_logic_vector and bit_vector and vice-versa;
functions rising_edge and falling_edge
for edge detection of signals.
x-value detection functions, is_x,
which detect values 'U', 'X', 'Z', 'W', '-' in the actual parameter.
See std_logic and std_logic_vector
The Std_Logic_1164 Package is copyrighted and may not be altered
(either by modifying/removing existing declarations or adding new ones).
In order to use any of the declarations of the Std_Logic_1164
package, the 'library' and 'use' clauses have to be used: