A set of values and a set of operations.
type type_name is type_definition;
Each object in VHDL has to be of some type, which defines possible
values and operations that can be performed on this object (and other
objects of the same type). The set of operations of a type consists of:
explicitly declared subprograms that have a parameter or result of
the particular type; such subprograms can be either predefined (in
standard packages) or user-defined;
basic operations (assignments, allocators, selected names, indexed
names, slice names)
numeric literals, literal null,
string literal, bit string literals, aggregates or predefined
attributes - depending on particular type.
There are four classes of types in VHDL:
scalar types (values of
these types have no elements),
composite types (values of
these types consist of element values),
access types (provide
access to objects of a given type) and
files (provide access to
objects that contain a sequence of values of a given type).
See respective topics for details.
Apart from predefined types (available through the packages Standard
and Std_Logic_1164), the
user can define his/her own types. A user-defined type can be of any
of the four classes mentioned above. The rules for defining types are
described in detail in the corresponding topics.
A type defines not only a set of values, but also a set of operators.
VHDL is strongly typed language which causes that two types defined
in exactly the same way (i.e. lexically identical) but differing only
by names will be considered different.
If a translation from one type to another is required, then type
conversion must be applied, even if the two types are very
similar (like assigning a natural variable to an integer variable).